Building a stronger European semiconductor ecosystem with the European Network of Chips Competence Centers
About aCCCess
aCCCess (Alliance of Chips Competence Centres for Enhanced Semiconductor Services) is a four-year Coordination and Support Action launched in March 2025 under the EU Chips Act. It aims to build a strong, interconnected European Network of Chips Competence Centres (ENCCC) that enables innovation, facilitates access to advanced semiconductor services, and strengthens Europe’s position in the global semiconductor value chain.
Network
Our network is comprised of Chip Competence Centers, Pilot lines and Design Platforms. Together, PLs and the DP empower the CCCs with cutting-edge infrastructure.
What is a Competence Center?
A Chips Competence Centre (CCC)is a hub of excellence providing access to specialised semiconductor knowledge, training, prototyping, testing, and small-scale production. These centres are pivotal to Europe's semiconductor strategy by:
- Supporting SMEs and start-ups with innovation services
- Bridging the gap between research and industry
- Promoting regional and pan-European know-how in chips and microelectronics
What is a Pilot Line & a Design Platform?
Pilot Lines (PLs) are advanced manufacturing facilities that help scale innovations from research to production, enabling validation in relevant environments.
The Design Platform (DP) is a cloud-based virtual environment providing state-of-the-art Electronic Design Automation (EDA) tools and design libraries to:
- Accelerate chip design and prototyping
- Enable collaboration across Europe
- Support education and skills development in semiconductor design
Latest News
Chips from the North: Connecting Design and Manufacturing in Europe
On 23-24 March, the Chips from the North event in Helsinki, organised by FiCCC, brought together Europe's semiconductor community to explore available support for companies across the value chain....
ENCCC Annual Meeting: Strengthening Europes Semiconductor Network
First Annual Meeting of CCCs was held on 5-6 February in Brussels...
PIXSpain Competence Centre Webpage Content Available
We are pleased to announce that the PIXSpain Competence Centre webpage is now fully available, providing a comprehensive overview of our role, activities, and ecosystem engagement within the photonics ecosystem....
Open Calls
EuroCDP Venture Development Programme
Opens:Apr 08, 2026 00:00 CEST
Closes:May 01, 2026 17:00 CEST
The EuroCDP launched its Venture Building Programmes, a dedicated acceleration and incubation track designed to help European fabless startups move faster, design smarter, and validate their first silicon with confidence.
CHIPS JU ECS Calls
Closes:May 07, 2026 17:00 CET
The Chips JU has two open calls for proposals under its Electronic Components & Systems (ECS) programme, funded through Horizon Europe. Deadline for project outline is 7 May 2026!
Chips Venture Forum 2026
Opens:Mar 17, 2026 09:00 CET
Closes:May 12, 2026 18:00 CET
The 2026 edition of the Chips Venture Forum will introduce an enhanced format designed to maximize interactions with investors and increase visibility across the semiconductor ecosystem.
Events
INTERMAG 2026
Apr 13, 2026 10:00 CETApr 13, 2026 12:00 CET
The worlds largest conference on magnetism.NanoIC is proud to be present at INTERMAG 2026, the worlds largest conference on magnetism, taking place April 1317, 2026 in Manchester, UK. The event brings together 1,5002,000 attendees and covers the latest research across the broad spectrum of fundamental and applied magnetism. The program...
Technology Offers Webinar-1
Apr 14, 2026 10:00 CESTApr 14, 2026 11:00 CEST
Webinar
Join us on April 14 for the launch of a new aCCCess webinar series spotlighting Europe's leading Pilot Lines and Chips Competence Centers within the aCCCess project. During the next 6 months, discover each month how these key infrastructures are shaping the future of microelectronics by presenting their technology offers...
Event hosted by
DATE 2026
Apr 20, 2026 09:00 CESTApr 22, 2026 17:00 CEST
Palazzo della Gran GuardiaVerona, Italy
## Design, Automation and Test in Europe Conference *The European Event for Electronic System Design & Test* The DATE conference is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test, and manufacturing of electronic circuits and systems....
Event hosted by
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Arago has reached a significant milestone with the tape-out of its first AI chip. This development could considerably influence competition in the semiconductor market.
CEA and PSMC Integrate RISC-V and Silicon Photonics into 3D Stacking
CEA-Leti and CEA-List have established a strategic partnership with Powerchip Semiconductor Manufacturing Corporation (PSMC) to advance the development of next-generation artificial intelligence systems. This collaboration focuses on the technical integration of RISC-V processor architectures and microLED-based silicon photonics into PSMC's established 3D stacking and interposer platforms. The primary objective is to address the intensifying bottlenecks [...]The post CEA and PSMC Integrate RISC-V and Silicon Photonics into 3D Stacking appeared first on Embedded.
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.