Building a stronger European semiconductor ecosystem with the European Network of Chips Competence Centers
About aCCCess
aCCCess (Alliance of Chips Competence Centres for Enhanced Semiconductor Services) is a four-year Coordination and Support Action launched in March 2025 under the EU Chips Act. It aims to build a strong, interconnected European Network of Chips Competence Centres (ENCCC) that enables innovation, facilitates access to advanced semiconductor services, and strengthens Europe’s position in the global semiconductor value chain.
Network
Our network is comprised of Chip Competence Centers, Pilot lines and Design Platforms. Together, PLs and the DP empower the CCCs with cutting-edge infrastructure.
What is a Competence Center?
A Chips Competence Centre (CCC) is a hub of excellence providing access to specialised semiconductor knowledge, training, prototyping, testing, and small-scale production. These centres are pivotal to Europe's semiconductor strategy by:
- Supporting SMEs and start-ups with innovation services
- Bridging the gap between research and industry
- Promoting regional and pan-European know-how in chips and microelectronics
What is a Pilot Line & a Design Platform?
Pilot Lines (PLs) are advanced manufacturing facilities that help scale innovations from research to production, enabling validation in relevant environments.
The Design Platform (DP) is a cloud-based virtual environment providing state-of-the-art Electronic Design Automation (EDA) tools and design libraries to:
- Accelerate chip design and prototyping
- Enable collaboration across Europe
- Support education and skills development in semiconductor design
Latest News
Training videos on YouTube
Upskill yourself for free with the learning videos produced by the Austrian Chips Competence Center. The first are already available on YouTube and will later be part of a full online course....
Chips Venture Forum 2025 Award... and the winner is Vertical Compute
The Chips Venture Forum 2025, organised by aCCCess and operated by Blumorpho in collaboration with the European Innovation Council and the European Commission, concluded on the 18 November 2025 at Messe Munich alongside SEMICON Europa bringing together Europes most promising semiconductor innovators and leading deep-tech investors....
Chips Venture Forum
Are you building the future of semiconductors, AI-powered systems, advanced materials, or edge computing? Benefit from the strengths of Competence Centres across Europe by joining a vibrant ecosystem of innovators and key stakeholders. This is your chance to accelerate your ideas and connect with experts in the semiconductor value chain....
Events
ECS Brokerage Event 2026
Feb 04, 2026 09:00 CETFeb 05, 2026 17:00 CET
The EGG, BrusselsRue Bara 175, 1070 Bruxelles
The ECS Brokerage Event combines the brokerage activities of the industry associations AENEAS, EPoSS and INSIDE into one networking event dedicated to project proposals for the new Chips JU Calls. This event gathers the ECS community around project ideas, allowing it to network, build consortia and start creating project proposals. The 2026...
Event hosted by
Official inauguration of the NanoIC pilot line
Feb 08, 2026 10:00 CETFeb 08, 2026 12:00 CET
This event will bring together key stakeholders to celebrate this major milestone for Europes semiconductor ecosystem. On February 9, 2026, imec will host the official inauguration of the NanoIC pilot line at its headquarters in Leuven, Belgium. This event will bring together key figures from the European semiconductor community, including...
Official inauguration of the NanoIC pilot line
Feb 09, 2026 09:30 CETFeb 09, 2026 13:00 CET
imec1Kapeldreeef 75, Leuven
This event will bring together key stakeholders to celebrate this major milestone for Europes semiconductor ecosystem. On February 9, 2026, imec will host the official inauguration of the NanoIC pilot line at its headquarters in Leuven, Belgium. This event will bring together key figures from the European semiconductor community, including...
Event hosted by
Latest Trends
MPL and Fraunhofer applying SiC to PICs
In the ALP-4-SiC project – Atomic Layer Processing for SiC for Applications in Photonics and Quantum Communication – researchers from the Max Planck
CEA-Leti’s open access pilot line
CEA-Leti’s €830 million FAMES semiconductor pilot line in Grenoble has been inaugurated. It is running FD-SOI wafers for RF, NVmemories and PMICs. The
Lightmatter and Cadence are accelerating the development of optical interconnect technologies in AI infrastructure.
Lightmatter, a leader in photonic computing, today announced a technology collaboration with Cadence, a major electronic design automation (EDA) provider, to jointly develop next-generation co-packaged optics (CPO) solutions.
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.