Building a stronger European semiconductor ecosystem with the European Network of Chips Competence Centers
About aCCCess
aCCCess (Alliance of Chips Competence Centres for Enhanced Semiconductor Services) is a four-year Coordination and Support Action launched in March 2025 under the EU Chips Act. It aims to build a strong, interconnected European Network of Chips Competence Centres (ENCCC) that enables innovation, facilitates access to advanced semiconductor services, and strengthens Europe’s position in the global semiconductor value chain.
Network
Our network is comprised of Chip Competence Centers, Pilot lines and Design Platforms. Together, PLs and the DP empower the CCCs with cutting-edge infrastructure.
What is a Competence Center?
A Chips Competence Centre (CCC) is a hub of excellence providing access to specialised semiconductor knowledge, training, prototyping, testing, and small-scale production. These centres are pivotal to Europe's semiconductor strategy by:
- Supporting SMEs and start-ups with innovation services
- Bridging the gap between research and industry
- Promoting regional and pan-European know-how in chips and microelectronics
What is a Pilot Line & a Design Platform?
Pilot Lines (PLs) are advanced manufacturing facilities that help scale innovations from research to production, enabling validation in relevant environments.
The Design Platform (DP) is a cloud-based virtual environment providing state-of-the-art Electronic Design Automation (EDA) tools and design libraries to:
- Accelerate chip design and prototyping
- Enable collaboration across Europe
- Support education and skills development in semiconductor design
Latest News
ENCCC Annual Meeting: Strengthening Europes Semiconductor Network
First Annual Meeting of CCCs was held on 5-6 February in Brussels...
PIXSpain Competence Centre Webpage Content Available
We are pleased to announce that the PIXSpain Competence Centre webpage is now fully available, providing a comprehensive overview of our role, activities, and ecosystem engagement within the photonics ecosystem....
Training videos on YouTube
Upskill yourself for free with the learning videos produced by the Austrian Chips Competence Center. The first are already available on YouTube and will later be part of a full online course....
Open Calls
APECS Open Access Call
Opens:Apr 01, 2026 00:00 CET
Closes:Jun 30, 2026 23:59 CET
The APECS Pilot Line launches it's first annual Open Access Calls!
As part of the APECS pilot lines broader access strategy, the annual Open Access Calls invite players across the semiconductor value chain to submit project ideas for selected pilot line technologies. The calls provide structured, guided, and transparent access to APECS modern R&D infrastructure, enabling companies, RTOs and universities to validate concepts, accelerate development, and collaborate directly with APECS experts.
Open Access to FAMES Pilot Line
Opens:Mar 09, 2026 00:00 CET
Closes:Dec 31, 2026 23:59 CET
The FAMES Pilot Line accepts Spontaneous User Requests year-round, offering organisations rapid access to its advanced semiconductor technologies outside the annual Open-Access Calls. This pathway enables time-critical projects to move forward without waiting for the next call.
Events
2nd APECS EU-Roadshow: Finland
Mar 23, 2026 12:00 CETMar 24, 2026 15:15 CET
Business FinlandPorkkalankatu 1, Helsinki
The pilot line for **Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems (APECS)** is a central initiative within the EU Chips Act. It aims to accelerate innovation in chiplet technologies and strengthen Europes semiconductor research and manufacturing capabilities. This workshop will highlight the activities of the APECS pilot line...
Event hosted by
EU-funded access to Infrachip infrastructures for SMEs, large companies and research institutes
Mar 24, 2026 14:00 CETMar 24, 2026 15:00 CET
Webinar
Working on semiconductor research or early-stage chip development in Europe? Then this upcoming webinar by Silicon Saxony might be highly relevant for you. The session will introduce INFRACHIP (https://infrachip.eu/) an EU-funded platform designed to open up advanced semiconductor research infrastructure across Europe. Heres what it offers: - Free access to state-of-the-art infrastructure...
Event hosted by
Advanced PDK workshop: N2 and A14 nanosheet pathfinding and applications
Mar 25, 2026 09:00 CETMar 26, 2026 16:00 CET
Imec 1Kapeldreef 75, Leuven, Belgium
## In-depth workshop on advanced CMOS technology nodes (N2 and A14), co-organized by Europractice and the NanoIC pilot line. ### Training information This two-day event combines theoretical insights with practical design experience, using two different EDA tools: Cadence and Synopsys.Why join?Gain early design experience on the most advanced CMOS technology...
Event hosted by
Latest Trends
Samsung targets 2nm process for HBM4E base die to boost AI chip edge
Samsung Electronics is reportedly planning to adopt a 2-nanometer (nm) process for the base die of its next-generation high-bandwidth memory (HBM), HBM4E, aiming to enhance its technological competitiveness. Industry experts see this as part of Samsung's broader strategy to leverage its advantage as a leading integrated device manufacturer (IDM) in the global AI semiconductor race.
The ten largest semiconductor foundries exceeded $169.5 billion in 2025
The ten largest semiconductor foundries exceeded $169.5 billion in 2025, driven by AI.
These Are The 100 Most Promising European Startups, According to Leading VCs
VivaTech, one of Europe's largest events for startups and technology, has published the new edition of the ranking "Top 100 Rising European Startups". The
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.