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How RIBER is expanding beyond III-V epitaxy to enable the next generation of photonic devices....

The Industrial Alliance for Semiconductors brings together Europes key microelectronics stakeholders through dedicated working groups addressing strategic challenges. One of these groups focuses on PFAS in semiconductor manufacturing, tackling the balance between environmental concerns and industrial needs. A new white paper outlines research priorities to support this transition....

The European Chips Act 2.0, presented on 3 June 2026, shifts the focus to demand for European chips. ChipNL CC reflects on what this means for the Dutch semiconductor ecosystem....

Opens:Jul 07, 2026 09:00 CET
Closes:Sep 30, 2026 17:00 CET
New Chips JU calls now open for applications, worth over 300 million in EU funding.
The calls span the two pillars of the programme: Electronic Components and Systems (ECS), which funds research and innovation projects, and the Chips for Europe Initiative, which funds capacity building and infrastructure.

Opens:Mar 09, 2026 00:00 CET
Closes:Dec 31, 2026 23:59 CET
The FAMES Pilot Line accepts Spontaneous User Requests year-round, offering organisations rapid access to its advanced semiconductor technologies outside the annual Open-Access Calls. This pathway enables time-critical projects to move forward without waiting for the next call.

Opens:Jun 02, 2026 00:00 CET
Closes:Jan 21, 2027 17:00 CET
Xecs is an Eureka Cluster specifically designed to accelerate the pace of sustainable industrial innovation in the Electronics Components & Systems (ECS) community. Xecs intends to create an ambitious international collaboration programme. The resulting RD&I projects will generate high societal and economic impact for all those who participate in an Xecs project.

Aug 24, 2026 09:00 CESTAug 28, 2026 12:00 CEST
Imec, Leuven, Belgium
This course will provide a thorough introduction to the ASIC design and development flow, covering multiple aspects, such as basics of Digital and Analog Design, Packaging, Test, Chiplet Integration, and IP-related challenges. All sessions will be given by experts from imec. This course is aimed at students with a professional Bachelor's...
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Sep 07, 2026 10:00 CETSep 07, 2026 12:00 CET
Palma de MallorcaSpain
The premier European forum for sharing innovations in solid-state devices and circuitsESSERC provides an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. With the level of integration for system-on-chip design rapidly increasing, a deeper interaction among technologists, device experts, IC designers and...
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Sep 07, 2026 12:00 EESTSep 08, 2026 21:00 EEST
Dipoli Conference CentreOtakaari 24, 02150 Espoo, Finland
Are you ready to explore the vision for Europe's semiconductor and quantum future with leading players in chips and chip-based systems? [The Nordic Chip Summit 2026](https://lyyti.events/p/nordic_chip_summit_2026) will take place on 7-8 September 2026 in Espoo, Finland, bringing together top experts, decision-makers, and innovators from across Europe and beyond. ...
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Chipmaking equipment supplier Lam Research to spend $3B+ on new labs - SiliconANGLE

More than 68,000 students have been trained in semiconductor chip design and 254 chip designs have been successfully taped out under the government's Chips to Start-ups (C2S) Programme as per the Ministry of Electronics and Information Technology. The programme is aimed at building an industry-ready talent pool and strengthening chip design capabilities in the country as India expands its domestic semiconductor ecosystem. In a release issued on Friday, the Ministry said, "More than 68,000 students have been trained under the programme so far." The C2S Programme aims to generate 85,000 industry-ready professionals at B.Tech, M.Tech and PhD levels specialising in semiconductor chip design. The Ministry said the programme was initiated for "capacity-building across the country and to address the issue of workforce talent gap and chip design infrastructure in the semiconductor design area." Apart from training students, participating academic institutions have successfully taped out 254 chip designs. Tape-out refers to the stage when a completed chip design is sent to a semiconductor foundry for manufacturing. "Participating institutions have successfully taped out 254 chip designs, comprising 175 designs at the 180 nm technology node at SCL, Mohali, and 79 designs at overseas semiconductor foundries," the Ministry said. The government has also provided 332 academic institutions across the country with access to advanced Electronic Design Automation (EDA) tools used for designing and developing semiconductor chips. These include tools from companies such as Synopsys, Cadence, Siemens EDA, Ansys, Keysight, Silvaco and AMD-Xilinx, among others. The Ministry also highlighted semiconductor research projects being supported at academic institutions in Andhra Pradesh, including work on a secure RISC-V processor for cryptographic applications at IIT Tirupati and a hardware accelerator for high-performance computing and cyber-physical systems at IIITDM Kurnool. Other projects include an energy-efficient neuromorphic processor for edge Internet of Things applications at NIT Andhra Pradesh and a memory-efficient co-processing unit for edge artificial intelligence applications at Shri Vishnu Engineering College for Women, Bhimavaram. "The projects are currently at various stages of design and development," the Ministry said, adding that depending on their scope and maturity, they are expected to progress towards prototype validation, including tape-out at semiconductor foundries wherever applicable. (ANI)

Republic of Korea will launch a 5tn won ($3.52 bn) semiconductor fund targeting promising chip materials, parts, equipment and fabless companies, a presidenti...

aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.