
European Materials Research Society Spring Meeting

Design, Automation and Test in Europe ConferenceThe European Event for Electronic System Design & Test

The world’s largest conference on magnetism.

Join us for an in-depth workshop on advanced CMOS technology nodes (N2 and A14), co-organized by Europractice and the NanoIC pilot line.

Navigating Geopolitics: Shaping Europe’s Semiconductor Future.

This event will bring together key stakeholders to celebrate this major milestone for Europe’s semiconductor ecosystem.

Connecting the ECS Community for Chips JU 2026 Collaboration.

Partner in the spotlight The NanoIC pilot line continues to grow its capabilities thanks to strong partner collaborations across Europe. One key contributor, Tyndall National Institute, offers deep expertise in simulation, materials processing, metrology, characterization, and fabrication, while pushing the boundaries of emerging materials integration into advanced CMOS platforms to deliver higher performance and energy efficiency.

Partner in the spotlight The NanoIC pilot line continues to grow its capabilities thanks to strong partner collaborations across Europe. One such partnership is with the Center for Surface Science and Nanotechnology (CSSNT) at the National University of Science and Technology Politehnica Bucharest (UPB). Together they are strengthening the NanoIC pilot line’s ability to perform advanced metrology on complex 3D structures at the atomic level.

Early November, we successfully moved ASML's TWINSCAN NXT:2150i – the most advanced deep ultraviolet (DUV) immersion lithography system available today – into imec's cleanroom. With enhanced overlay accuracy, improved critical dimension uniformity, and optimized system dynamics, the NXT:2150i supports NanoIC’s mission to push the boundaries of semiconductor scaling. What's more, with ASML’s full product portfolio being integrated into imec’s pilot line – including High-NA EUV – NanoIC can tap into the world's most advanced infrastructure for semiconductor R&D. While High-NA EUV will be used for the most demanding layers, the NXT:2150i will handle many less critical layers. Offering high throughput, the tool will accelerate imec’s capacity to develop and validate new process modules at industry-relevant dimensions, shortening learning cycles and speeding up the path from idea to prototype. Watch the video for a behind-the-scenes look at this exciting step forward ...

The Chips Venture Forum 2025, organised by aCCCess and operated by Blumorpho in collaboration with the European Innovation Council and the European Commission, concluded on the 18 November 2025 at Messe Munich alongside SEMICON Europa bringing together Europes most promising semiconductor innovators and leading deep-tech investors.

Featured in the media From 18 to 20 November, NanoIC joined the Chips Joint Undertaking booth at SEMICON Europa, showcasing how our pilot line accelerates semiconductor innovation in Europe. Accompanying our presence at the event, SEMI.org published an in-depth article on NanoIC’s pathfinding process design kits (P-PDKs) and how they bridge the gap between academia and industry to enable next-generation chip design. The article features insights from Professor Mehdi Tahoori (Karlsruhe Institute of Technology) and Anita Farokhnejad (DTCO Program Manager at imec), explaining why these kits are critical for Europe’s semiconductor ecosystem and how they empower researchers to innovate beyond 2 nanometer. Click to read the full SEMI.org article

Featured in the media
NanoIC’s pathfinding PDKs: accelerating design for future chips beyond 2nm technology.
Advances in AI and chip architectures are driving new demands in semiconductor design, making close collaboration between academia and industry essential.
However, as we move to advanced semiconductor technology nodes, academic research has gradually drifted away from industrial practice, limiting academic researchers in driving innovation.
NanoIC aims to bridge this gap, providing pathfinding PDKs, predictive, early-access design environments, enabling researchers to simulate and optimize future chip architectures.
By restoring the link between academic innovation and industrial practice, pathfinding PDKs accelerate disruptive ideas and help build a resilient, next-generation semiconductor ecosystem.
Featured in the media

Are you building the future of semiconductors, AI-powered systems, advanced materials, or edge computing? Benefit from the strengths of Competence Centres across Europe by joining a vibrant ecosystem of innovators and key stakeholders. This is your chance to accelerate your ideas and connect with experts in the semiconductor value chain.

Launched on 1 June 2025, the Hellenic Chips Competence Centre (HCCC) is Greece’s first semiconductor hub, established through a partnership between HETiA, the Ministry of Development, and the European Chips Joint Undertaking. With €7 million in funding, HCCC aims to strengthen Europe’s technological autonomy by supporting innovation, research, start-ups, and training in chip design and testing. As part of the EU’s “Chips for Europe” initiative, HCCC connects Greek academic and industrial sectors, focusing on specialized applications. It positions Greece as a digital technology hub in Southeastern Europe. HCCC’s initial actions will be presented at the HETiA Forum in December 2025.

The European semiconductor sector is experiencing significant growth, fueled by increasing investments in research and development. Companies are focusing on enhancing chip performance and energy efficiency to meet the needs of various industries.

The German electronics magazine Markt&Technik has published a detailed feature on the NanoIC pilot line, recognizing it as a cornerstone of Europes semiconductor strategy under the EU Chips Act.
The article follows the NanoIC workshop held at ITF World 2025 in Antwerp, where the projects vision and technological roadmap were presented to a broad audience of industry leaders and policymakers.

Click to watch

Watch the after movie of this memorable afternoon track on the second day of ITF World 2025.

aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.