Verification and Design Flow of Digital Chips
Experts from KU Leuven and companies active in the semiconductor industry will introduce the rationale, methodology, and key steps of the digital chip design flow through a combination of theoretical lectures and hands-on training sessions. It's organised on campus (not online) in Leuven.
Level
Intermediate
Delivery Mode
In person
Language
English
Dates
18 Mar 2027 – 13 May 2027
Duration
5-day course + evaluation in March-May 2027
Learning hours
0
ECTS
0.00
ECVET
0.00
Seats
Limited (20)
Location
Department of Electrical Engineering (ESAT), Kasteelpark Arenberg 10, 3001 Heverlee, Belgium
Fees
2900 (waiver possible)
Delivered by
KU leuven
Chips Competence Centre
FC3
Certification Type
Micro-credentials
Target Audience
Graduate students
Pre-requisites
This course is open to a rather broad technical audience. Participants must have a Master in a technical field or equivalent through professional experience. Applications are evaluated by the academic coordinator, based on the requested information in the application form.
Categories
ManufacturingIC DesignProcess
Registration Contact
Register Now
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.