Challenges in IC design for 6G: Fundamental SiGe BiCMOS Building Blocks
This workshop will explore the main challenges, techniques, and practical considerations involved in designing and integrating ICs at mm-Wave and sub-THz frequencies.
Level
Intermediate
Delivery Mode
In person
Language
English
Dates
4 Oct 2026
Learning hours
0
ECTS
0.00
ECVET
0.00
Seats
unlimited
Location
https://www.eumw.eu/general-information/
Fees
570
Delivered by
CADETTI
Chips Competence Centre
CADETTI
Certification Type
Certificate of Attendance
Target Audience
Graduate students
Pre-requisites
Understanding of integrated circuit design and semiconductor technologies
Familiarity with RF/microwave concepts
Categories
IC Design
Registration Contact
Register Now
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.