VHDL Fundamentals: Ontwerp en simuleer digitale hardware
An introduction to digital hardware design using VHDL. The course provides a practical introduction to the design of digital systems, starting from the fundamental concepts of combinational and sequential logic and progressing towards the description, simulation, and analysis of digital hardware.
Level
Introductory
Delivery Mode
In person
Language
Dutch
Dates
6 Oct 2026 – 15 Dec 2026
Duration
3 course days (October 6, November 17 and December 15, 2026)
Learning hours
24
ECTS
0.00
ECVET
0.00
Seats
unlimited
Location
Universiteit Antwerpen, Campus Groenenborger, Belgium
Fees
1200
Delivered by
UAntwerpen
Chips Competence Centre
FC3
Certification Type
Certificate of Attendance
Target Audience
Graduate students
Pre-requisites
basic knowledge of electronic circuits
Categories
IC Design
Registration Contact
Register Now
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.