Layout of Analog Chips
Instructors from multiple companies in the chip industry will learn you all about the layout of analog chips. The course offers theoretical sessions, and there will be a strong focus on hands-on training and real-life examples.
Level
Intermediate
Delivery Mode
In person
Language
English
Dates
19 Feb 2027 – 14 May 2027
Duration
8 course days + evaluation (February - May, 2027)
Learning hours
64
ECTS
3.00
ECVET
0.00
Seats
Limited (24)
Location
Department of Electrical Engineering (ESAT), Kasteelpark Arenberg 10, 3001 Heverlee, Belgium
Fees
4800 (waiver possible)
Delivered by
KU Leuven
Chips Competence Centre
FC3
Certification Type
Micro-credentials
Target Audience
Graduate students
Pre-requisites
This course is open for a rather broad technical audience. Participants must have a Bachelor or a Master in a technical field, or equivalent through professional work experience.
Categories
IC DesignProcessManufacturing
Registration Contact
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aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.