High-Level FPGA Design
Introduce high-level digital circuit synthesis and optimization from algorithms in the C/C++ language. It covers digital design description in programming languages, hardware-specific libraries, and design techniques. Practical experiments environment: AMD Vitis HLS and AMD (Xilinx).
Level
Introductory
Delivery Mode
In person
Language
English
Dates
1 Jun 2026 – 3 Jun 2026
Duration
24
Learning hours
0
ECTS
0.00
ECVET
0.00
Seats
Limited (8)
Location
slovenia, Ljubljana
Fees
0
Delivered by
CC Chip.si
Competence Centre
CC Chip.si
Certification Type
Certificate of Attendance
Target Audience
Recent graduates
Pre-requisites
Knowledge of digital electronics, knowledge of the C/C++ programming language.
Categories
IC Design
Registration Contact
Register Now
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.