FD-SOI RF Analog Design
This course is intended for participants interested in RF techniques applied to FD-SOI technologies. It combines lectures and labs to allow participants getting skills (knowledge and know-how)
Level
Advanced
Delivery Mode
In person
Language
English
Dates
10 Sept 2026 – 10 Sept 2026
Duration
1 day
Learning hours
7
ECTS
0.00
ECVET
0.00
Seats
Limited (12)
Location
CIME Nanotech, 3 parvis Louis Neel, 38016 Grenoble Cedex
Fees
Free for SME, Startup, academics and researchers. Fees for SMC and LG
Delivered by
University professor
Chips Competence Centre
ASTEERICS
Certification Type
Certificate of Attendance
Target Audience
Public
Pre-requisites
Classic RF analog design (Si)
Categories
IC Design
Registration Contact
Register Now
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.