Bare Metal Programming on RISC-V
A hands-on bare-metal course on the SiFive FE310-G002 RISC-V microcontroller (HiFive1), focused on interrupts, machine timers, and implementing a preemptive round-robin scheduler with full context switching in C and minimal RISC-V assembly.
Level
Intermediate
Delivery Mode
In person
Language
Slovene
Dates
30 Jun 2026 – 2 Jul 2026
Duration
3 days
Learning hours
12
ECTS
0.00
ECVET
0.00
Seats
Limited (30)
Location
Faculty of Computer and Information Science(UL FRI), 100 Ljubljana, Vecna pot 113, PR09
Fees
No fees as training is financed.
Delivered by
CC Chip.si
Chips Competence Centre
CC Chip.si
Certification Type
Certificate of Attendance
Target Audience
Mid-career professionals
Pre-requisites
A working knowledge of the C programming language (variables, functions, pointers, structs, and bitwise operators).
Basic assembly programming skills familiarity with registers, instructions, and the load/store model (prior RISC-V experience is helpful but not required; the relevant RISC-V instructions are introduced as needed).
Basic familiarity with how a microcontroller works (memory, registers, and peripherals) at an introductory level.
Categories
IC Design
Registration Contact
Register Now
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.