ASIC Design Training
A 5-day hands-on course on analog IC design, including schematic development, component sizing, verification across process, voltage, and temperature (PVT) variations, and layout design for fabrication.
Level
Advanced
Delivery Mode
In person
Language
Slovene
Dates
6 Jul 2026 – 10 Jul 2026
Duration
1 week
Learning hours
0
ECTS
0.00
ECVET
0.00
Seats
Limited (8)
Location
Faculty of Electrical Engineering, University of Ljubljana (UL FE), Trzaska cesta 25, Ljubljana
Fees
Free of charge.
Delivered by
CC Chip.si
Chips Competence Centre
CC Chip.si
Certification Type
Certificate of Attendance
Target Audience
Mid-career professionals
Pre-requisites
Participants are expected to have knowledge of Cadence Virtuoso EDA including cell hierarchy, schematic design, adexl simulations, test creation for simulations (tran, ac, dc sweep, Monte Carlo), corner analysis and basic layout knowledge (layer definitions, DRC, LVS, parasitic extraction).
Categories
IC Design
Registration Contact
Register Now
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.