Towards robust source/drain modules for advanced logic devices

Paper in the spotlight

Papers in the spotlight

At recent international and European conferences, imec experts demonstrated progress in improving process steps and modules that will facilitate baseline flows for advanced logic devices – cornerstones of the NanoIC pilot line for beyond-2nm systems on chip.

Four of these conference papers highlight key process steps for enabling source/drain modules for nanosheet and CFET devices: source/drain epitaxial layer growth and contact silicide formation. Frank Holsteyns, Vice President R&D unit process and modules at imec: 

“Developing high-quality source/drain epitaxial layers and low-resistance silicide contacts remains a significant challenge for these devices, primarily because of their high-aspect-ratio vertical structures and high device densities. Within the framework of NanoIC, imec’s epi team has made remarkable progress in developing these critical process steps, which are among the key building blocks of the nanosheet and CFET baseline flows. Key hurdles addressed include managing lateral growth on non-(001) surfaces and ensuring a pristine surface condition prior to epitaxy.”

The results are described in more detail in the papers:

Schematic representation and TEM images of Si1-xGex:B source/drain-contact formation in nanosheet device structures.

This work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union’s Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania.