Backside power delivery networks to support advanced logic technology nodes
Research update
The semiconductor industry is currently advancing toward mass production of the 2nm technology node, in which gate-all-around (GAA) nanosheet transistors play a central role.
GAA nanosheet technology is expected to last for at least three technology generations before chip makers transition to the complementary FET (or CFET) technology. Developing the baselines for these advanced logic transistor architectures is at the heart of the NanoIC pilot line.
The introduction of these advanced technologies into the logic roadmap will be supported by innovations in the chip’s back-end-of-line (BEOL) and by new ways to power the transistors.
One of these are backside power delivery networks (BSPDNs). With a BSPDN, the power distribution network is moved to the wafer’s backside where the power delivering interconnects can be made larger and less resistant. This innovative concept was pioneered by imec in 2019 and supports NanoIC’s mission in developing advanced logic flows.
Interested in learning more about BSPDN? Read about imec’s recent design-technology co-optimization (DTCO) study, highlighting the benefits BSPDNs bring to logic use cases (i.e., always-on and switched-domain designs). The results were presented at the 2025 Symposium on VLSI Technology and Circuits.
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.