
Discover how NanoICs IGZObased eDRAM PDK can accelerate your nextgeneration memory designs in a oneday workshop, co-organized by Europractice and the NanoIC pilot line. Training informationThis workshop introduces the key foundations, materials, design principles, and potential applications behind NanoICs IGZObased eDRAM PDK. Through the day, participants move from exploring the broader memory landscape to understanding the practical implementation of eDRAM architectures with IGZO-based technology, covering oxidesemiconductor fundamentals, device behaviour, reliability, and designtechnology cooptimization.Extra bonus: This event directly precedes NanoICs Advanced Interconnect PDK training on May 27th, 2026. We highly recommend combining both sessions to gain a broader understanding of interconnect technologies right after deepdiving into IGZObased eDRAM. Why join this eDRAM workshop?Gain a solid understanding of IGZObased eDRAM, from device physics to circuitlevel behaviour, to accelerate your learning curve for advanced memory technologies.Translate theory into design insights, with practical guidance on how to apply the PDK in exploratory design and simulation flows to evaluate eDRAM architectures.Engage with imec experts developing the underlying technology and get answers to your technical questions.Prepare for advanced technology nodes, understanding the cooptimization challenges and opportunities when integrating eDRAM into future chip platforms.Get an exclusive guided window tour of imecs existing 300mm cleanroom.Agenda (technical presentations)Memory landscape, system needs, emerging memoriesMaterial deposition, morphology, and properties of IGZOTransport, material selection rules, and doping for IGZO devicesEtch development for enabling semiconductor-based eDRAMIGZO device fundamentals, optimization, and applicationsIGZO integration and test vehicles for material screening learningsFundamental aspects of IGZO reliabilityDTCO for 2T0C and 3T0C IGZO eDRAM memoriesSensing schemes for 2T0C IGZO eDRAMIGZO eDRAM PDK: what and howWho should attend? Design talents from both academia and industry; such as IC designers, researchers, MSc and PhD students, post-docs, professors, and companies interested in advanced memory solutions.Attendance fee100 EURDate May 26, 9 am 6 pm Venue Imec 1, Kapeldreef 75, Leuven, BelgiumRegistrationEuropractice member can register via the Europractice website.Non-Europractice members can register via imec.academy.Imec employees can register here through the internal portal.Registration will close on 11 May 2026, or earlier if all available places are filled.Note: Before attending this course: All participants should have the imec eDRAM DKLA signed by their hiring institutions. Please contact our support team at imecpdk@imec.be and mpc@imec.be with the mention that you would like access to the imec eDRAM PDK for training purposes. Our team will guide you through the procedure. Depending on the country of the requesting institution, the access procedure may take longer. Please contact the aforementioned email accounts for further information.

aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
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