Advanced PDK workshop: N2 and A14 nanosheet pathfinding and applications

In-depth workshop on advanced CMOS technology nodes (N2 and A14), co-organized by Europractice and the NanoIC pilot line.

Training information

This two-day event combines theoretical insights with practical design experience, using two different EDA tools: Cadence and Synopsys.Why join?Gain early design experience on the most advanced CMOS technology nodes (N2 and A14), including nanosheet devices, and backside power delivery networks.Hands-on exposure: learn practical design flows using Cadence and Synopsys.Explore disruptive features such as SRAM memory macros, updated design rules, and system-level integration strategies for beyond-2nm technologies.Connect with experts from imec, Europractice, and the NanoIC pilot line to discuss future technology roadmaps and design enablement.

Who should attend? Design talents from both academia and industry; such as IC designers, researchers, MSc and PhD students, post-docs, professors, and companies preparing for advanced nodes.

Dates

• March 25, 9 am - 4 pm (seminars): 100 seats
• March 26, 9 am - 4 pm (hands-on workshop): 25 seats

Venue

Imec 1, Kapeldreef 75, Leuven, Belgium

Registration

The registration fee for this event is EUR 150. Registration will close on 15 March 2026, or earlier if all available places are filled, It is also possible to attend just the first day.