Building a stronger European semiconductor ecosystem with the European Network of Chips Competence Centers
About aCCCess
aCCCess (Alliance of Chips Competence Centres for Enhanced Semiconductor Services) is a four-year Coordination and Support Action launched in March 2025 under the EU Chips Act. It aims to build a strong, interconnected European Network of Chips Competence Centres (ENCCC) that enables innovation, facilitates access to advanced semiconductor services, and strengthens Europe’s position in the global semiconductor value chain.
Network
Our network is comprised of Chip Competence Centers, Pilot lines and Design Platforms. Together, PLs and the DP empower the CCCs with cutting-edge infrastructure.
What is a Competence Center?
A Chips Competence Centre (CCC) is a hub of excellence providing access to specialised semiconductor knowledge, training, prototyping, testing, and small-scale production. These centres are pivotal to Europe's semiconductor strategy by:
- Supporting SMEs and start-ups with innovation services
- Bridging the gap between research and industry
- Promoting regional and pan-European know-how in chips and microelectronics
What is a Pilot Line & a Design Platform?
Pilot Lines (PLs) are advanced manufacturing facilities that help scale innovations from research to production, enabling validation in relevant environments.
The Design Platform (DP) is a cloud-based virtual environment providing state-of-the-art Electronic Design Automation (EDA) tools and design libraries to:
- Accelerate chip design and prototyping
- Enable collaboration across Europe
- Support education and skills development in semiconductor design
Latest News
Chips Venture Forum 2025 Award... and the winner is Vertical Compute
The Chips Venture Forum 2025, organised by aCCCess and operated by Blumorpho in collaboration with the European Innovation Council and the European Commission, concluded on the 18 November 2025 at Messe Munich alongside SEMICON Europa bringing together Europes most promising semiconductor innovators and leading deep-tech investors....
Chips Venture Forum
Are you building the future of semiconductors, AI-powered systems, advanced materials, or edge computing? Benefit from the strengths of Competence Centres across Europe by joining a vibrant ecosystem of innovators and key stakeholders. This is your chance to accelerate your ideas and connect with experts in the semiconductor value chain....
Greek chips at the heart of innovation
Launched on 1 June 2025, the Hellenic Chips Competence Centre (HCCC) is Greece’s first semiconductor hub, established through a partnership between HETiA, the Ministry of Development, and the European Chips Joint Undertaking. With €7 million in funding, HCCC aims to strengthen Europe’s technological autonomy by supporting innovation, research, start-ups, and...
Open Calls
Open Access to FAMES Pilot Line
Opens:Dec 31, 2024 23:00 CET
Closes:Dec 31, 2025 22:59 CET
The FAMES Pilot Line accepts Spontaneous User Requests year-round, offering organisations rapid access to its advanced semiconductor technologies outside the annual Open-Access Calls. This pathway enables time-critical projects to move forward without waiting for the next call.
Xecs Call 5
Closes:Jan 22, 2026 17:00 CET
Xecs Call 5 is open! Submit your Project Outline by 22 January 2026 (17:00 CET)!
Events
SINTEF's PiezoMEMS Platform Training
Jan 14, 2026 10:00 CETJan 15, 2026 16:30 CET
ImecLeuven, Belgium
This two-day training program provides participants with both a solid theoretical foundation and extensive hands-on practice in piezoMEMS technologies. The course is structured to gradually guide learners from fundamental principles to practical applications. Day 1: participants are introduced to the core concepts of MEMS (Micro-Electro-Mechanical Systems), the science of piezoelectric materials,...
Event hosted by
FAMES European FD-SOI Design School (EFDS)
Jan 25, 2026 09:00 CETJan 30, 2026 17:00 CET
CIME Nanotech and CEA-Leti Grenoble, France
The FAMES European FD-SOI Design School (EFDS) is a one-week theoretical and practical training course focused on FD-SOI design. This course is intended for chip designers, engineers, Masters and PhD students, with the purpose of providing the essential scientific and technical foundations for developing integrated circuits using FD-SOI technology. ...
Event hosted by
ECS Brokerage Event 2026
Feb 04, 2026 09:00 CETFeb 05, 2026 17:00 CET
The EGG, BrusselsRue Bara 175, 1070 Bruxelles
The ECS Brokerage Event combines the brokerage activities of the industry associations AENEAS, EPoSS and INSIDE into one networking event dedicated to project proposals for the new Chips JU Calls. This event gathers the ECS community around project ideas, allowing it to network, build consortia and start creating project proposals. The 2026...
Event hosted by
Latest Trends
CEA-Leti and ST demo path to fully monolithic silicon RF front-ends with 3D sequential integration
Wafer-level assembly of SiGe HBT, RF SOI and passive technologies allows dense co-integration of best-in class functions
Chiplet Technology in Automotive Applications: A Cost-Effective Path to Advanced Electronics
Let us emphasize first and foremost the economic case for chiplet architecture in the automotive systems. The automotive industry faces an unprecedented challenge: integrating increasingly sophisticated electronic systems while maintaining cost competitiveness in mass production. Traditional monolithic System-on-Chip (SoC) designs, while functionally robust, present significant economic barriers when scaled to automotive volumes. Chiplet technology emerges [...]The post Chiplet Technology in Automotive Applications: A Cost-Effective Path to Advanced Electronics appeared first on Embedded.
Generative AI In Chip Manufacturing
How it works, what it can do, and what can go wrong.
aCCCess has received funding from the European Union’s Digital Europe Chips JU under Grant Agreement No 101217840.
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or [name of the granting authority]. Neither the European Union nor the granting authority can be held responsible for them.